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FPGA · Development Board
Lattice iCEstick Evaluation Kit
A USB-stick evaluation board for the low-power iCE40HX-1K FPGA. Two unpopulated 1x10 expansion headers (J1, J3) and a populated 2x6 Digilent Pmod (J2) break out 24 FPGA I/Os, alongside five LEDs, an IrDA transceiver, and an FT2232H for USB programming. It was one of the first boards to gain open-source (Project IceStorm) toolchain support.
Processor
Lattice iCE40HX1K-TQ144 (144-pin TQFP, 1,280 LUTs, 2 PLLs)
Logic
3.3 V LVCMOS I/O (not 5 V tolerant)
Power
USB-A bus powered (5 V); on-board regulators provide 3.3 V and 1.2 V
Format
USB-stick PCB with a male USB-A edge, two 1x10 headers, and one 2x6 Pmod
Check before wiring
- All FPGA I/O are 3.3 V LVCMOS and are not 5 V tolerant; level-shift any 5 V signals.
- J1 and J3 ship as unpopulated 1x10 footprints; confirm pin 1 from the EB82 silkscreen before soldering headers.
- On the J2 Pmod, positions 5/11 are GND and 6/12 are 3.3 V — they are power-only, not FPGA I/O.
- JTAG/SPI configuration is routed through the FT2232H and is not exposed on the expansion headers; CRESET is tied to the bridge.
Interfaces
GPIOSPIUARTJTAGUSB
Source-backed connector
Interactive pin map
Pin map
Connector
J1 / J3 expansion headers and J2 Pmod connector
Signals grouped by function — schematic layout, not to physical scale
Dense header — open Full view for a roomier, fully-labelled diagram.
Simplified diagram, grouped by function — not to physical scale. Pin data is source-backed; verify against the linked documentation.
Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.
- Header signal names and iCE40HX1K TQ144 package pins are from EB82 Tables 1-3; FPGA pin numbers cross-checked against the canonical iCEstick.pcf constraint file.
- J1 and J3 are unpopulated 1x10 footprints; solder your own headers and confirm pin 1 from the EB82 silkscreen before wiring.
- J2 is a populated 2x6 Digilent Pmod: positions 5/11 are GND and 6/12 are 3.3 V; the eight remaining positions are FPGA I/O.
- All I/O are 3.3 V LVCMOS and are not 5 V tolerant. JTAG/SPI configuration runs through the on-board FT2232H and is not broken out to these headers.
All 32 pins (table)
| # | Signal | Role | Net | Also / notes |
|---|---|---|---|---|
| J1 - Bank 0 | ||||
| 1 | Power | 3V3 | ||
| 2 | Ground | GND | ||
| 3 | GPIO | |||
| 4 | GPIO | |||
| 5 | GPIO | |||
| 6 | GPIO | |||
| 7 | GPIO | |||
| 8 | GPIO | |||
| 9 | GPIO | |||
| 10 | GPIO | |||
| J3 - Bank 2 | ||||
| 1 | Power | 3V3 | ||
| 2 | Ground | GND | ||
| 3 | GPIO | |||
| 4 | GPIO | |||
| 5 | GPIO | |||
| 6 | GPIO | |||
| 7 | GPIO | |||
| 8 | GPIO | |||
| 9 | GPIO | |||
| 10 | GPIO | |||
| J2 - Pmod (Bank 1) | ||||
| 1 | GPIO | |||
| 2 | GPIO | |||
| 3 | GPIO | |||
| 4 | GPIO | |||
| 5 | Ground | GND | ||
| 6 | Power | 3V3 | ||
| 7 | GPIO | |||
| 8 | GPIO | |||
| 9 | GPIO | |||
| 10 | GPIO | |||
| 11 | Ground | GND | ||
| 12 | Power | 3V3 | ||
Why it matters
- iCE40HX1K: 1,280 LUTs, two PLLs, and 64 kbit embedded block RAM in a compact TQFP-144.
- Self-contained USB-A stick form factor — plugs directly into a host port, no external supply.
- J1 + J3 expose 16 general-purpose I/Os (Banks 0 and 2); J2 is a standard 2x6 Digilent Pmod with 8 I/Os.
- On-board FT2232H provides both the JTAG/SPI programming channel and a USB-UART bridge.
- Five user LEDs and an IrDA transceiver wired to dedicated FPGA pins.
- First-class open-source flow via Project IceStorm / Yosys / nextpnr in addition to Lattice iCEcube2.
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