Lattice iCEstick Evaluation Kit

Lattice Semiconductor · iCE40

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Showing 32 of 32 pins

Simplified diagram, grouped by function — not to physical scale. Pin data is source-backed; verify against the linked documentation.

Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.

Header signal names and iCE40HX1K TQ144 package pins are from EB82 Tables 1-3; FPGA pin numbers cross-checked against the canonical iCEstick.pcf constraint file.
J1 and J3 are unpopulated 1x10 footprints; solder your own headers and confirm pin 1 from the EB82 silkscreen before wiring.
J2 is a populated 2x6 Digilent Pmod: positions 5/11 are GND and 6/12 are 3.3 V; the eight remaining positions are FPGA I/O.
All I/O are 3.3 V LVCMOS and are not 5 V tolerant. JTAG/SPI configuration runs through the on-board FT2232H and is not broken out to these headers.

Loading source-backed pinouts…

Lattice Semiconductor · iCE40

Filter pins

Showing 32 of 32 pins

Simplified diagram, grouped by function — not to physical scale. Pin data is source-backed; verify against the linked documentation.

Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.

Header signal names and iCE40HX1K TQ144 package pins are from EB82 Tables 1-3; FPGA pin numbers cross-checked against the canonical iCEstick.pcf constraint file.
J1 and J3 are unpopulated 1x10 footprints; solder your own headers and confirm pin 1 from the EB82 silkscreen before wiring.
J2 is a populated 2x6 Digilent Pmod: positions 5/11 are GND and 6/12 are 3.3 V; the eight remaining positions are FPGA I/O.
All I/O are 3.3 V LVCMOS and are not 5 V tolerant. JTAG/SPI configuration runs through the on-board FT2232H and is not broken out to these headers.