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FPGA · Development Board
Lattice CrossLink-NX Evaluation Board
An evaluation board for the CrossLink-NX LIFCL-40 FPGA, targeting video bridging, imaging, and edge-AI designs. Three Digilent-compatible Pmod headers (J17, J18, J19) provide a general-purpose GPIO breakout alongside an FMC LPC connector, a Raspberry Pi GPIO header, MIPI CSI-2 camera connectors, a D-PHY header, and a PCIe x1 interface. It is supported by Lattice Radiant software.
Processor
Lattice LIFCL-40-9BG400C (CrossLink-NX, 28 nm FD-SOI Nexus, 400-ball caBGA)
Logic
3.3 V on the Pmod banks; 1.2-1.8 V on the camera / MIPI banks
Power
USB-B for programming; separate 12 V jack for PCIe and full-board power
Format
~100 x 80 mm PCB with FMC LPC, Raspberry Pi GPIO, MIPI/D-PHY, and three Pmod headers
Check before wiring
- The Pmod map applies to the LIFCL-40-9BG400C board documented in FPGA-EB-02028.
- Pmod headers are 3.3 V; the camera, D-PHY, and MIPI banks run at 1.2-1.8 V and are not interchangeable with 3.3 V Pmod accessories.
- On each Pmod, positions 5/11 are GND and 6/12 are 3.3 V per the Digilent standard — only the eight signal positions are device-connected.
- The FMC VADJ rail is jumper-selectable; set it before attaching FMC modules.
- A 12 V supply is required for PCIe and full-power operation; USB-B alone powers only the programming path.
Interfaces
GPIOSPII2CJTAGUSBCSIPCIe
Source-backed connector
Interactive pin map
Pin map
Connector
J17, J18, and J19 Pmod expansion headers
Signals grouped by function — schematic layout, not to physical scale
Dense header — open Full view for a roomier, fully-labelled diagram.
Simplified diagram, grouped by function — not to physical scale. Pin data is source-backed; verify against the linked documentation.
Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.
- Pmod I/O signal names and LIFCL-40 caBGA balls are from FPGA-EB-02028 Table 8.6; each header is a 2x6 Digilent Pmod exposing eight FPGA I/O.
- Per the Digilent Pmod 1.2.0 standard, positions 5/11 are GND and 6/12 are 3.3 V; only the eight signal positions are device-connected.
- These Pmod banks are the board's general-purpose breakout. Camera, D-PHY, and MIPI interfaces run at 1.2-1.8 V and are not interchangeable with 3.3 V Pmod accessories.
- The board needs its 12 V supply for PCIe and full-power operation; USB-B alone powers only the programming path.
All 36 pins (table)
| # | Signal | Role | Net | Also / notes |
|---|---|---|---|---|
| J17 - PMOD0 | ||||
| 1 | GPIO | |||
| 2 | GPIO | |||
| 3 | GPIO | |||
| 4 | GPIO | |||
| 5 | Ground | GND | ||
| 6 | Power | 3V3 | ||
| 7 | GPIO | |||
| 8 | GPIO | |||
| 9 | GPIO | |||
| 10 | GPIO | |||
| 11 | Ground | GND | ||
| 12 | Power | 3V3 | ||
| J18 - PMOD1 | ||||
| 1 | GPIO | |||
| 2 | GPIO | |||
| 3 | GPIO | |||
| 4 | GPIO | |||
| 5 | Ground | GND | ||
| 6 | Power | 3V3 | ||
| 7 | GPIO | |||
| 8 | GPIO | |||
| 9 | GPIO | |||
| 10 | GPIO | |||
| 11 | Ground | GND | ||
| 12 | Power | 3V3 | ||
| J19 - PMOD2 | ||||
| 1 | GPIO | |||
| 2 | GPIO | |||
| 3 | GPIO | |||
| 4 | GPIO | |||
| 5 | Ground | GND | ||
| 6 | Power | 3V3 | ||
| 7 | GPIO | |||
| 8 | GPIO | |||
| 9 | GPIO | |||
| 10 | GPIO | |||
| 11 | Ground | GND | ||
| 12 | Power | 3V3 | ||
Why it matters
- CrossLink-NX LIFCL-40: 40K logic cells on the 28 nm FD-SOI Nexus platform with instant-on configuration.
- Three independent Digilent Pmod headers (J17/J18/J19), each on a different I/O bank, for GPIO breakout.
- FMC LPC connector and a Raspberry Pi GPIO header for high-density and HAT-style expansion.
- MIPI CSI-2 camera connectors and a D-PHY header for imaging and video-bridging pipelines.
- On-board PCIe x1 Gen2 interface and FTDI-based USB-B JTAG programming.
- Developed with Lattice Radiant; well-suited to sensor-bridging and low-power vision designs.
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