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Microcontroller · Development Board
Flipper Zero
A pocket multi-tool for hardware and RF work whose 18-pin top header exposes STM32WB55 GPIO, UART, SWD, and 1-Wire — widely used as an interactive bench tool for probing and bring-up.
Processor
STM32WB55RG — Arm Cortex-M4 @ 64 MHz application core plus a Cortex-M0+ radio co-processor
Logic
3.3 V I/O, 20 mA per pin, 5 W total across all I/O
Power
Internal LiPo with USB-C charging; switchable 5 V and 3.3 V outputs on the header
Format
Handheld multi-tool with an 18-pin 2.54 mm header on the top edge
Check before wiring
- Header I/O is 3.3 V only — it is not 5 V tolerant. Level-shift anything driven from 5 V logic.
- Pins 10 (PA14/SWCLK) and 12 (PA13/SWDIO) are the SWD debug lines. Driving them as general I/O will interfere with debugging and firmware flashing.
- Pin 1 (+5 V) is off by default and must be enabled in the GPIO settings menu; expecting 5 V there without enabling it is a common bring-up mistake.
- Respect the documented budget: 20 mA per pin and 5 W total across all I/O pins, with a 1.2 A ceiling on the 3.3 V rail.
- Pin 17 (PB14) is shared with the onboard iButton / 1-Wire front end, so external use can conflict with that function.
- Hardware revisions exist; this map is transcribed from the current firmware target for the F7 (STM32WB55) main board.
Interfaces
GPIOI2CSPIUARTADCPWMUSBBluetoothSWD
Source-backed connector
Interactive pin map
Pin map
Connector
18-pin GPIO header (top edge)
Signals grouped by function — schematic layout, not to physical scale
Dense header — open Full view for a roomier, fully-labelled diagram.
Simplified diagram, grouped by function — not to physical scale. Pin data is source-backed; verify against the linked documentation.
Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.
- Single row of 18 pins along the top edge, numbered 1-18 left to right with the screen facing you.
- I/O is 3.3 V. Each pin can source up to 20 mA, and total consumption across all I/O pins must not exceed 5 W.
- Pin 1 (+5 V) is disabled by default and has to be switched on in the GPIO settings menu; pin 9 (+3.3 V) is on by default with a 1.2 A maximum load.
- Pins 10 and 12 are the STM32WB55 SWD debug lines (SWCLK and SWDIO) — using them as general I/O conflicts with debugging and flashing.
All 18 pins (table)
| # | Signal | Role | Net | Also / notes |
|---|---|---|---|---|
| GPIO header (pins 1-18) | ||||
| 1 | Power | 5V | Disabled by default — enable via GPIO settings. Output, not an input. | |
| 2 | GPIO | ADC-capable; also on TIM1, so usable for PWM. | ||
| 3 | GPIO | ADC-capable. | ||
| 4 | GPIO | ADC-capable; also on LPTIM2. | ||
| 5 | GPIO | |||
| 6 | GPIO | |||
| 7 | GPIO | ADC-capable. | ||
| 8 | Ground | GND | ||
| 9 | Power | 3V3 | Enabled by default; 1.2 A maximum load. | |
| 10 | Debug | SWD | SWCLK · SWD clock. Repurposing this pin breaks debugger/flashing access. | |
| 11 | Ground | GND | ||
| 12 | Debug | SWD | SWDIO · SWD data. Repurposing this pin breaks debugger/flashing access. | |
| 13 | UART | UART | USART TX | |
| 14 | UART | UART | USART RX | |
| 15 | GPIO | ADC-capable. | ||
| 16 | GPIO | ADC-capable. | ||
| 17 | Alt | iButton · Shared with the onboard iButton / 1-Wire front end. | ||
| 18 | Ground | GND | ||
Why it matters
- 18-pin header brings out GPIO, UART, SPI, I2C, 1-Wire, and the full SWD debug interface on a device you can hold.
- STM32WB55 pairs a Cortex-M4 application core with a dedicated Cortex-M0+ Bluetooth LE radio core.
- Switchable 5 V and 3.3 V rails on the header can power a small target directly.
- Pin-to-STM32-port mapping is published in the firmware's own resource table, so it can be verified against the code that runs on the device.
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