Flipper Zero

Flipper Devices · Flipper Zero

Filter pins

Showing 18 of 18 pins

Simplified diagram, grouped by function — not to physical scale. Pin data is source-backed; verify against the linked documentation.

Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.

Single row of 18 pins along the top edge, numbered 1-18 left to right with the screen facing you.
I/O is 3.3 V. Each pin can source up to 20 mA, and total consumption across all I/O pins must not exceed 5 W.
Pin 1 (+5 V) is disabled by default and has to be switched on in the GPIO settings menu; pin 9 (+3.3 V) is on by default with a 1.2 A maximum load.
Pins 10 and 12 are the STM32WB55 SWD debug lines (SWCLK and SWDIO) — using them as general I/O conflicts with debugging and flashing.

Full pin list, synchronized with the board drawing.
#	Role	Net	Also / notes
GPIO header (pins 1-18)
1	Power	5V	Disabled by default — enable via GPIO settings. Output, not an input.
2	GPIO		ADC-capable; also on TIM1, so usable for PWM.
3	GPIO		ADC-capable.
4	GPIO		ADC-capable; also on LPTIM2.
5	GPIO
6	GPIO
7	GPIO		ADC-capable.
8	Ground	GND
9	Power	3V3	Enabled by default; 1.2 A maximum load.
10	Debug	SWD	SWCLK · SWD clock. Repurposing this pin breaks debugger/flashing access.
11	Ground	GND
12	Debug	SWD	SWDIO · SWD data. Repurposing this pin breaks debugger/flashing access.
13	UART	UART	USART TX
14	UART	UART	USART RX
15	GPIO		ADC-capable.
16	GPIO		ADC-capable.
17	Alt		iButton · Shared with the onboard iButton / 1-Wire front end.
18	Ground	GND

Loading source-backed pinouts…

Flipper Devices · Flipper Zero

Filter pins

Showing 18 of 18 pins

Simplified diagram, grouped by function — not to physical scale. Pin data is source-backed; verify against the linked documentation.

Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.

Single row of 18 pins along the top edge, numbered 1-18 left to right with the screen facing you.
I/O is 3.3 V. Each pin can source up to 20 mA, and total consumption across all I/O pins must not exceed 5 W.
Pin 1 (+5 V) is disabled by default and has to be switched on in the GPIO settings menu; pin 9 (+3.3 V) is on by default with a 1.2 A maximum load.
Pins 10 and 12 are the STM32WB55 SWD debug lines (SWCLK and SWDIO) — using them as general I/O conflicts with debugging and flashing.

Full pin list, synchronized with the board drawing.
#	Role	Net	Also / notes
GPIO header (pins 1-18)
1	Power	5V	Disabled by default — enable via GPIO settings. Output, not an input.
2	GPIO		ADC-capable; also on TIM1, so usable for PWM.
3	GPIO		ADC-capable.
4	GPIO		ADC-capable; also on LPTIM2.
5	GPIO
6	GPIO
7	GPIO		ADC-capable.
8	Ground	GND
9	Power	3V3	Enabled by default; 1.2 A maximum load.
10	Debug	SWD	SWCLK · SWD clock. Repurposing this pin breaks debugger/flashing access.
11	Ground	GND
12	Debug	SWD	SWDIO · SWD data. Repurposing this pin breaks debugger/flashing access.
13	UART	UART	USART TX
14	UART	UART	USART RX
15	GPIO		ADC-capable.
16	GPIO		ADC-capable.
17	Alt		iButton · Shared with the onboard iButton / 1-Wire front end.
18	Ground	GND