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Microcontroller · Development Board
NXP FRDM-KL25Z Rev. E
A Cortex-M0+ teaching platform used in embedded-systems and microprocessor laboratories, with onboard OpenSDA debugging, an accelerometer, capacitive touch, and a position-complete Rev. E expansion map.
Processor
MKL25Z128VLK4 Arm Cortex-M0+ @ 48 MHz, 128 KB flash
Logic
3.3 V GPIO (not 5 V tolerant)
Power
OpenSDA USB, KL25Z USB, 4.3-9 V VIN, or regulated 1.71-3.6 V
Format
Arduino R3-compatible board with four dual-row I/O headers
Check before wiring
- All GPIO is 3.3 V and not 5 V tolerant; only J9-10 is a 5 V rail and J9-16 is the 4.3-9 V VIN input.
- Older NXP pinout material swaps PTE0/PTE1. NXP's quick-reference card and support correction establish J2-18 = PTE0/SDA and J2-20 = PTE1/SCL.
- PTD1 on J2-12/D13 also drives the onboard blue RGB LED, so the LED circuit loads that signal.
- PTA4 on J1-10/D4 has NMI_b as its reset-state function; configure the port mux before treating it as GPIO.
- This entry targets Rev. E. Rev. D has different power, OpenSDA isolation, USB-host, and VREFH circuitry even though the main I/O placement is similar.
Interfaces
GPIOI2CSPIUARTADCDACPWMUSBSWD
Source-backed connector
Interactive pin map
Pin map
Connector
J1, J2, J9, and J10 I/O headers (Rev. E)
Signals grouped by function — schematic layout, not to physical scale
Dense header — open Full view for a roomier, fully-labelled diagram.
Simplified diagram, grouped by function — not to physical scale. Pin data is source-backed; verify against the linked documentation.
Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.
- Header positions are shown in ascending designator order; view the board from the component side with the USB connectors at the bottom.
- The even-numbered outer rows implement the Arduino R3 shield footprint; the odd-numbered inner rows expose additional KL25Z signals.
- All MCU I/O is 3.3 V and is not 5 V tolerant. VIN on J9-16 accepts 4.3-9 V; the 3.3 V pins accept only a regulated 1.71-3.6 V source.
- J2-18 = PTE0/SDA and J2-20 = PTE1/SCL follows NXP's corrected mapping, not the swapped assignments in the older pinout spreadsheet.
All 64 pins (table)
| # | Signal | Role | Net | Also / notes |
|---|---|---|---|---|
| J1 I/O header (2x8) | ||||
| 1 | SPI | SPI | SPI0_MISO / SPI0_MOSI / CMP0_IN1 | |
| 2 | UART | UART | D0 / UART0_RX / FTM2_CH0 | |
| 3 | ADC | ADC0_SE14 / TSI0_CH13 | ||
| 4 | UART | UART | D1 / UART0_TX / FTM2_CH1 | |
| 5 | UART | UART | UART1_RX / FTM0_CH2 / CLKOUT | |
| 6 | GPIO | D2 / SPI1_PCS0 / UART2_RX / FTM0_CH4 | ||
| 7 | SPI | SPI | SPI0_PCS0 / UART1_TX / FTM0_CH3 | |
| 8 | PWM | D3 / FTM1_CH0 | ||
| 9 | SPI | SPI | SPI0_SCK / LPTMR0_ALT2 / CMP0_OUT | |
| 10 | GPIO | D4 / I2C1_SDA / FTM0_CH1 / NMI_b · NMI_b is the reset-state function; configure the pin mux before using it as ordinary GPIO. | ||
| 11 | SPI | SPI | SPI0_MOSI / SPI0_MISO / CMP0_IN0 | |
| 12 | PWM | D5 / FTM0_CH2 | ||
| 13 | I2C | I2C | I2C1_SCL | |
| 14 | PWM | D6 / I2C0_SCL / FTM0_CH4 / CMP0_IN2 | ||
| 15 | I2C | I2C | I2C1_SDA | |
| 16 | PWM | D7 / I2C0_SDA / FTM0_CH5 / CMP0_IN3 | ||
| J2 I/O header (2x10) | ||||
| 1 | GPIO | FTM_CLKIN0 | ||
| 2 | PWM | D8 / FTM1_CH1 | ||
| 3 | GPIO | FTM_CLKIN1 | ||
| 4 | PWM | D9 / FTM0_CH5 / SPI1_SCK / UART2_TX / ADC0_SE6b | ||
| 5 | GPIO | |||
| 6 | SPI | SPI | D10 / SPI0_PCS0 / FTM0_CH0 | |
| 7 | GPIO | |||
| 8 | SPI | SPI | D11 / SPI0_MOSI / UART2_RX / FTM0_CH2 | |
| 9 | SPI | SPI | SPI0_MOSI / SPI0_MISO | |
| 10 | SPI | SPI | D12 / SPI0_MISO / UART2_TX / FTM0_CH3 | |
| 11 | SPI | SPI | SPI0_MISO / SPI0_MOSI | |
| 12 | SPI | SPI | D13 / SPI0_SCK / ADC0_SE5b / FTM0_CH1 · Also drives the onboard blue RGB LED cathode; LED loading affects this header signal. | |
| 13 | PWM | FTM0_CH4 | ||
| 14 | Ground | GND | ||
| 15 | Reserved | No connection. | ||
| 16 | Power | VREFH | AREF · VREFH is tied to 3.3 V by default. Supplying external AREF requires the Rev. E resistor/jumper modification documented by NXP. | |
| 17 | ADC | ADC0_SE7b / SPI1_MOSI / UART0_RX | ||
| 18 | I2C | I2C | D14 / SDA / I2C1_SDA / UART1_TX · Corrected NXP mapping: J2-18 is PTE0. | |
| 19 | GPIO | SPI1_MISO / UART0_TX | ||
| 20 | I2C | I2C | D15 / SCL / I2C1_SCL / UART1_RX · Corrected NXP mapping: J2-20 is PTE1. | |
| J9 I/O and power header (2x8) | ||||
| 1 | GPIO | EXTRG_IN | ||
| 2 | Reserved | RFU · Reserved in the Arduino R3 compatibility chart; do not use as ordinary I/O. | ||
| 3 | GPIO | |||
| 4 | Power | P3V3 | IOREF | |
| 5 | SPI | SPI | SPI1_PCS0 | |
| 6 | System | RESET_b | ||
| 7 | SPI | SPI | SPI1_SCK | |
| 8 | Power | 3V3 | 3.3V | |
| 9 | SPI | SPI | SPI1_SCK | |
| 10 | Power | 5V | 5V | |
| 11 | SPI | SPI | SPI1_MISO / SPI1_MOSI | |
| 12 | Ground | GND | ||
| 13 | SPI | SPI | SPI1_PCS0 | |
| 14 | Ground | GND | ||
| 15 | GPIO | |||
| 16 | Power | P5_9V_VIN | VIN · Regulated board input; NXP specifies 4.3-9 V. | |
| J10 analog and auxiliary header (2x6) | ||||
| 1 | ADC | ADC0_DP0 / ADC0_SE0 / FTM1_CH0 / UART0_TX | ||
| 2 | ADC | A0 / ADC0_SE8 / I2C0_SCL / FTM1_CH0 | ||
| 3 | ADC | ADC0_DM0 / ADC0_SE4a / FTM1_CH1 / UART0_RX | ||
| 4 | ADC | A1 / ADC0_SE9 / I2C0_SDA / FTM1_CH1 | ||
| 5 | ADC | ADC0_DP3 / ADC0_SE3 / FTM2_CH0 / UART2_TX | ||
| 6 | ADC | A2 / ADC0_SE12 / I2C0_SCL / FTM2_CH0 | ||
| 7 | ADC | ADC0_DM3 / ADC0_SE7a / FTM2_CH1 / UART2_RX | ||
| 8 | ADC | A3 / ADC0_SE13 / I2C0_SDA / FTM2_CH1 | ||
| 9 | ADC | ADC0_SE4b / CMP0_IN5 / FTM0_CH2 | ||
| 10 | I2C | I2C | A4 / SDA / I2C1_SDA / ADC0_SE11 / FTM0_CH1 | |
| 11 | DAC | DAC0_OUT / ADC0_SE23 / CMP0_IN4 / FTM0_CH3 | ||
| 12 | I2C | I2C | A5 / SCL / I2C1_SCL / ADC0_SE15 / FTM0_CH0 | |
Why it matters
- OpenSDA supplies drag-and-drop programming, CMSIS-DAP debugging, and a virtual serial port.
- Arduino R3-compatible outer rows plus inner rows expose 53 MCU I/O signals.
- Onboard MMA8451Q accelerometer, RGB LED, and capacitive touch slider support self-contained labs.
- Used as the target platform in university embedded-system architecture and optimization courses.
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