Loading source-backed pinouts…
Microcontroller · Development Board
ESP32-S3-DevKitM-1
The MINI-module counterpart to the ESP32-S3-DevKitC-1. It exposes the same 44 header positions but in a different order — GPIO0-GPIO18 run sequentially down J1, while the flash/PSRAM bus and JTAG pins sit on J3.
Processor
ESP32-S3-MINI-1 / MINI-1U module (dual-core 32-bit Xtensa LX7, Wi-Fi + Bluetooth LE 5)
Logic
3.3 V GPIO
Power
USB, or the 5 V or 3.3 V header pins (use only one source at a time)
Format
Dual-header breadboard dev kit, 22 pins per side
Check before wiring
- Do NOT reuse ESP32-S3-DevKitC-1 wiring or overlays on this board. Both have 44 header pins, but the position-to-signal mapping diverges from J1 pin 2 onward — for example J1 pin 4 is GPIO2 here and GPIO4 on the DevKitC-1.
- GPIO0, GPIO3, GPIO45, and GPIO46 are ESP32-S3 boot strapping pins. Espressif's header table for this board does not flag them, so the risk is easy to miss — cross-check the ESP32-S3 datasheet before driving them at reset.
- GPIO33-GPIO37 and GPIO26 are consumed by the module's SPI flash/PSRAM bus on octal-PSRAM variants (SPIIO4-SPIIO7, SPIDQS, SPICS1). Using them as general I/O on those modules will corrupt memory access.
- GPIO43/GPIO44 are the default UART0 console and flashing pins.
- Espressif documents this as the first released revision of the board, so no alternative header revision exists — but confirm you have a MINI board and not a WROOM DevKitC-1 before wiring.
Interfaces
GPIOI2CSPIUARTADCPWMUSBWi-FiBluetoothJTAG
Source-backed connector
Interactive pin map
Pin map
Connector
ESP32-S3-DevKitM-1 J1/J3 headers
USB at the bottom, component side up, headers on both edges
Simplified technical illustration. Pin data is source-backed; verify against the linked documentation before wiring.
Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.
- Espressif's user guide states this is the first revision of the board released, so there are no revision-to-revision header differences to reconcile.
- This header map is NOT interchangeable with the ESP32-S3-DevKitC-1 (WROOM) map. Both expose 44 pins, but the position-to-signal assignment differs from J1 pin 2 onward.
- GPIO0, GPIO3, GPIO45, and GPIO46 are ESP32-S3 boot strapping pins. This board's own header table does not mark them as such — the strapping behaviour comes from the ESP32-S3 datasheet.
- GPIO33-GPIO37 carry the octal SPI flash/PSRAM bus (SPIIO4-SPIIO7, SPIDQS) on octal-PSRAM module variants and are not free for user I/O there.
- GPIO19/GPIO20 double as native USB D-/D+.
All 44 pins (table)
| # | Signal | Role | Net | Also / notes |
|---|---|---|---|---|
| 1 | Power | 3V3 | ||
| 2 | System | Strapping · RTC_GPIO0. Boot strapping pin per the ESP32-S3 datasheet. | ||
| 3 | ADC | RTC_GPIO1, TOUCH1, ADC1_CH0 | ||
| 4 | ADC | RTC_GPIO2, TOUCH2, ADC1_CH1 | ||
| 5 | System | Strapping · RTC_GPIO3, TOUCH3, ADC1_CH2. Boot strapping pin per the ESP32-S3 datasheet. | ||
| 6 | ADC | RTC_GPIO4, TOUCH4, ADC1_CH3 | ||
| 7 | ADC | RTC_GPIO5, TOUCH5, ADC1_CH4 | ||
| 8 | ADC | RTC_GPIO6, TOUCH6, ADC1_CH5 | ||
| 9 | ADC | RTC_GPIO7, TOUCH7, ADC1_CH6 | ||
| 10 | ADC | RTC_GPIO8, TOUCH8, ADC1_CH7, SUBSPICS1 | ||
| 11 | SPI | SPI | RTC_GPIO9, TOUCH9, ADC1_CH8, FSPIHD, SUBSPIHD | |
| 12 | SPI | SPI | RTC_GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4, SUBSPICS0 | |
| 13 | SPI | SPI | RTC_GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5, SUBSPID | |
| 14 | SPI | SPI | RTC_GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6, SUBSPICLK | |
| 15 | SPI | SPI | RTC_GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7, SUBSPIQ | |
| 16 | SPI | SPI | RTC_GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS, SUBSPIWP | |
| 17 | UART | UART | RTC_GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P | |
| 18 | UART | UART | RTC_GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N | |
| 19 | UART | UART | RTC_GPIO17, U1TXD, ADC2_CH6 | |
| 20 | UART | UART | RTC_GPIO18, U1RXD, ADC2_CH7, CLK_OUT3 | |
| 21 | Power | 5V | ||
| 22 | Ground | GND | ||
| 1 | Ground | GND | ||
| 2 | System | EN | ||
| 3 | System | Strapping · Boot strapping pin per the ESP32-S3 datasheet. | ||
| 4 | System | Strapping · Boot strapping pin per the ESP32-S3 datasheet. | ||
| 5 | UART | UART | U0RXD · CLK_OUT2. Default console/flashing UART. | |
| 6 | UART | UART | U0TXD · CLK_OUT1. Default console/flashing UART. | |
| 7 | Debug | JTAG | MTMS | |
| 8 | Debug | JTAG | MTDI · CLK_OUT1 | |
| 9 | Debug | JTAG | MTDO · CLK_OUT2 | |
| 10 | Debug | JTAG | MTCK · CLK_OUT3, SUBSPICS1 | |
| 11 | SPI | SPI | FSPIWP, SUBSPIWP | |
| 12 | Reserved | SPIDQS · FSPIQ, SUBSPIQ. Consumed by the octal PSRAM/flash bus on octal module variants. | ||
| 13 | Reserved | SPIIO7 · FSPICLK, SUBSPICLK. Consumed by the octal PSRAM/flash bus on octal module variants. | ||
| 14 | Reserved | SPIIO6 · FSPID, SUBSPID. Consumed by the octal PSRAM/flash bus on octal module variants. | ||
| 15 | Reserved | SPIIO5 · FSPICS0, SUBSPICS0. Consumed by the octal PSRAM/flash bus on octal module variants. | ||
| 16 | Reserved | SPIIO4 · FSPIHD, SUBSPIHD. Consumed by the octal PSRAM/flash bus on octal module variants. | ||
| 17 | Reserved | SPICS1 · Tied to the module's SPI flash/PSRAM chip select. | ||
| 18 | GPIO | RTC_GPIO21 | ||
| 19 | Alt | USB_D+ · RTC_GPIO20, U1CTS, ADC2_CH9, CLK_OUT1 | ||
| 20 | Alt | USB_D- · RTC_GPIO19, U1RTS, ADC2_CH8, CLK_OUT2 | ||
| 21 | Alt | SPICLK_N, SUBSPICLK_N_DIFF. Drives the onboard addressable RGB LED. | ||
| 22 | Alt | SPICLK_P, SUBSPICLK_P_DIFF |
Why it matters
- GPIO0-GPIO18 appear in strict numeric order down J1, which makes breadboard wiring far easier to reason about than the DevKitC-1 layout.
- Fourteen J1 pins carry a capacitive touch channel (TOUCH1-TOUCH14) alongside their ADC function.
- Native USB D+/D- (GPIO20/GPIO19) and an addressable RGB LED on GPIO48 are both broken out.
Keep exploring
Similar boards
Adafruit ESP32-S3 Feather
same development board class · same microcontroller platform
Adafruit Feather M4 Express
same microcontroller platform · 7 shared interfaces
Adafruit Feather nRF52840 Express
same development board class · same microcontroller platform
Adafruit Feather RP2040
same microcontroller platform · 7 shared interfaces