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Microcontroller · Development Board
ESP32-C61-DevKitC-1
Espressif's reference board for the ESP32-C61, a low-cost single-core RISC-V part with Wi-Fi 6 and Bluetooth LE 5. Both 16-pin headers are documented pin-by-pin in the official user guide.
Processor
ESP32-C61-WROOM-1 module (ESP32-C61, single-core 32-bit RISC-V, Wi-Fi 6 + Bluetooth LE 5)
Logic
3.3 V GPIO
Power
USB Type-C, or the 5 V or 3.3 V header pins (use only one source at a time)
Format
Dual-header breadboard-compatible dev kit, 16 pins per side
Check before wiring
- Revision risk: Espressif states that for boards with PW number PW-2025-05-0781 and later, "J1 and J3 functions are updated". This map is scoped to v2.0 — check the PW number printed on your board before wiring anything against it.
- GPIO7, GPIO8, and GPIO9 are strapping pins; their level at reset selects boot mode. Driving them at power-up can prevent the board from booting.
- J1 pin 11 is NOT a dependable GPIO. On modules with integrated SPI PSRAM the pad is already used as SPICS1 and cannot be repurposed; only modules without PSRAM expose it as GPIO14.
- J1 pin 16 and J3 pin 16 are NC (no connection) — they are not grounds and not spare I/O.
- GPIO3-GPIO7 double as the JTAG/flash lines (MTMS, MTDI, MTCK, MTDO, FSPI*). Avoid driving them externally while flashing or debugging.
Interfaces
GPIOI2CSPIUARTADCPWMUSBWi-FiBluetoothJTAG
Source-backed connector
Interactive pin map
Pin map
Connector
ESP32-C61-DevKitC-1 v2.0 J1/J3 headers
USB at the bottom, component side up, headers on both edges
Simplified technical illustration. Pin data is source-backed; verify against the linked documentation before wiring.
Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.
- Scoped to hardware revision v2.0 (PW number PW-2025-05-0781 and later); Espressif states that J1 and J3 functions were updated at that PW number, so earlier v1.0 boards differ.
- GPIO7, GPIO8, and GPIO9 are strapping pins.
- GPIO13/GPIO12 carry native USB D+/D-.
- J1 pin 11 is NC on modules without integrated SPI PSRAM, and GPIO14/SPICS1 (unavailable for user I/O) on modules with it.
All 32 pins (table)
| # | Signal | Role | Net | Also / notes |
|---|---|---|---|---|
| 1 | Power | 3V3 | ||
| 2 | System | High enables the chip, low disables it. | ||
| 3 | Debug | JTAG | MTDI · LP_GPIO4, ADC1_CH2, FSPIWP | |
| 4 | Debug | JTAG | MTCK · LP_GPIO5, ADC1_CH3 | |
| 5 | Debug | JTAG | MTDO · LP_GPIO6, FSPICLK | |
| 6 | System | Strapping · FSPID | ||
| 7 | GPIO | XTAL_32K_P, LP_GPIO0 | ||
| 8 | ADC | XTAL_32K_N, LP_GPIO1, ADC1_CH0 | ||
| 9 | System | Strapping · ZCD0, FSPICS0 | ||
| 10 | GPIO | |||
| 11 | Reserved | No connection on modules with integrated SPI PSRAM (the pad is consumed as SPICS1); usable as GPIO14 only on modules without PSRAM. | ||
| 12 | GPIO | LP_GPIO2, FSPIQ | ||
| 13 | Debug | JTAG | MTMS · LP_GPIO3, ADC1_CH1, FSPIHD | |
| 14 | Power | 5V | ||
| 15 | Ground | GND | ||
| 16 | Reserved | No connection. | ||
| 1 | Ground | GND | ||
| 2 | UART | UART | U0TXD | |
| 3 | UART | UART | U0RXD | |
| 4 | GPIO | |||
| 5 | GPIO | SDIO_DATA3 | ||
| 6 | GPIO | SDIO_DATA2 | ||
| 7 | GPIO | SDIO_DATA1 | ||
| 8 | GPIO | SDIO_DATA0 | ||
| 9 | GPIO | SDIO_CLK | ||
| 10 | GPIO | SDIO_CMD | ||
| 11 | System | Strapping · ZCD1 | ||
| 12 | Ground | GND | ||
| 13 | Alt | USB_D+ | ||
| 14 | Alt | USB_D- | ||
| 15 | Ground | GND | ||
| 16 | Reserved | No connection. |
Why it matters
- One of the first widely available ESP32-C61 breakouts, useful for evaluating Wi-Fi 6 on Espressif's low-cost RISC-V line.
- Six SDIO-capable pins (GPIO22-GPIO28) are broken out together on J3, unusual for a board this small.
- Native USB D+/D- reach the header on GPIO13/GPIO12 for device-mode work without an external bridge.
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