FPGA · Development Board

Digilent Nexys A7-100T

A feature-rich Artix-7 trainer used in digital-system design and computer-architecture laboratories, with five fully mapped Pmod ports, DDR2, Ethernet, USB HID, VGA, audio, and onboard I/O.

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Processor

AMD/Xilinx Artix-7 XC7A100T-1CSG324C FPGA

Logic

3.3 V LVCMOS on Pmod ports (not 5 V tolerant)

Power

USB or 4.5-5.5 V external supply; JP3 selects source

Format

FPGA trainer with five 2x6 Pmod expansion ports

Check before wiring

All Pmod I/O is 3.3 V and not 5 V tolerant. Pmod VCC and GND pairs can deliver up to 1 A according to the reference manual.
JA-JD signals are not impedance-controlled or delay-matched; do not use them as arbitrary high-speed differential links.
JXADC uses coupled analog-pair routing and unpopulated anti-alias capacitors; its routing can limit digital signal speed.
This entry is for the Nexys A7-100T/XC7A100T SKU. The Nexys A7-50T uses a different FPGA package and a different master XDC.
JP3 must match the chosen USB or external power source; the external input is 4.5-5.5 V, not the 7-15 V range used by some other Digilent boards.

Interfaces

GPIOI2CSPIUARTADCPWMUSBJTAGEthernet

Source-backed connector

Interactive pin map

Open full inspector

Pin map

Connector

JA, JB, JC, JD, and JXADC 2x6 Pmod ports

Signals grouped by function — schematic layout, not to physical scale

Full view

Dense header — open Full view for a roomier, fully-labelled diagram.

Simplified diagram, grouped by function — not to physical scale. Pin data is source-backed; verify against the linked documentation.

Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.

Positions follow the front view of each right-angle connector as loaded on the PCB: signals 1-4 and 7-10, GND on 5/11, and 3.3 V on 6/12.
JA-JD are 3.3 V LVCMOS general-purpose Pmods. Their traces are not impedance-controlled or length-matched.
JXADC pairs positions 1/7, 2/8, 3/9, and 4/10 for XADC analog input; its coupled routing and partially loaded filters can limit digital speed.
Specialized USB, Ethernet, microSD, VGA, audio, JTAG, and programming connectors are intentionally excluded from this student-expansion map.

All 60 pins (table)

Full pin list, synchronized with the board drawing.
#	Role	Net	Also / notes
Pmod JA
1	GPIO		FPGA C17
2	GPIO		FPGA D18
3	GPIO		FPGA E18
4	GPIO		FPGA G17
5	Ground	GND
6	Power	3V3
7	GPIO		FPGA D17
8	GPIO		FPGA E17
9	GPIO		FPGA F18
10	GPIO		FPGA G18
11	Ground	GND
12	Power	3V3
Pmod JB
1	GPIO		FPGA D14
2	GPIO		FPGA F16
3	GPIO		FPGA G16
4	GPIO		FPGA H14
5	Ground	GND
6	Power	3V3
7	GPIO		FPGA E16
8	GPIO		FPGA F13
9	GPIO		FPGA G13
10	GPIO		FPGA H16
11	Ground	GND
12	Power	3V3
Pmod JC
1	GPIO		FPGA K1
2	GPIO		FPGA F6
3	GPIO		FPGA J2
4	GPIO		FPGA G6
5	Ground	GND
6	Power	3V3
7	GPIO		FPGA E7
8	GPIO		FPGA J3
9	GPIO		FPGA J4
10	GPIO		FPGA E6
11	Ground	GND
12	Power	3V3
Pmod JD
1	GPIO		FPGA H4
2	GPIO		FPGA H1
3	GPIO		FPGA G1
4	GPIO		FPGA G3
5	Ground	GND
6	Power	3V3
7	GPIO		FPGA H2
8	GPIO		FPGA G4
9	GPIO		FPGA G2
10	GPIO		FPGA F3
11	Ground	GND
12	Power	3V3
Pmod JXADC (dual analog/digital)
1	ADC		FPGA A13 / AD3P / XA_P1
2	ADC		FPGA A15 / AD10P / XA_P2
3	ADC		FPGA B16 / AD2P / XA_P3
4	ADC		FPGA B18 / AD11P / XA_P4
5	Ground	GND
6	Power	3V3
7	ADC		FPGA A14 / AD3N / XA_N1
8	ADC		FPGA A16 / AD10N / XA_N2
9	ADC		FPGA B17 / AD2N / XA_N3
10	ADC		FPGA A18 / AD11N / XA_N4
11	Ground	GND
12	Power	3V3

Why it matters

XC7A100T FPGA provides 101,440 logic cells and 4.86 Mbit of block RAM.
Four digital Pmods plus one dual analog/digital XADC Pmod expose 40 FPGA signals.
Onboard switches, buttons, LEDs, eight-digit display, VGA, audio, Ethernet, and USB HID support full lab sequences without extra hardware.
Digilent publishes an exact Nexys A7-100T master XDC file for reproducible package-pin constraints.

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Loading source-backed pinouts…

Full pin list, synchronized with the board drawing.
#	Role	Net	Also / notes
Pmod JA
1	GPIO		FPGA C17
2	GPIO		FPGA D18
3	GPIO		FPGA E18
4	GPIO		FPGA G17
5	Ground	GND
6	Power	3V3
7	GPIO		FPGA D17
8	GPIO		FPGA E17
9	GPIO		FPGA F18
10	GPIO		FPGA G18
11	Ground	GND
12	Power	3V3
Pmod JB
1	GPIO		FPGA D14
2	GPIO		FPGA F16
3	GPIO		FPGA G16
4	GPIO		FPGA H14
5	Ground	GND
6	Power	3V3
7	GPIO		FPGA E16
8	GPIO		FPGA F13
9	GPIO		FPGA G13
10	GPIO		FPGA H16
11	Ground	GND
12	Power	3V3
Pmod JC
1	GPIO		FPGA K1
2	GPIO		FPGA F6
3	GPIO		FPGA J2
4	GPIO		FPGA G6
5	Ground	GND
6	Power	3V3
7	GPIO		FPGA E7
8	GPIO		FPGA J3
9	GPIO		FPGA J4
10	GPIO		FPGA E6
11	Ground	GND
12	Power	3V3
Pmod JD
1	GPIO		FPGA H4
2	GPIO		FPGA H1
3	GPIO		FPGA G1
4	GPIO		FPGA G3
5	Ground	GND
6	Power	3V3
7	GPIO		FPGA H2
8	GPIO		FPGA G4
9	GPIO		FPGA G2
10	GPIO		FPGA F3
11	Ground	GND
12	Power	3V3
Pmod JXADC (dual analog/digital)
1	ADC		FPGA A13 / AD3P / XA_P1
2	ADC		FPGA A15 / AD10P / XA_P2
3	ADC		FPGA B16 / AD2P / XA_P3
4	ADC		FPGA B18 / AD11P / XA_P4
5	Ground	GND
6	Power	3V3
7	ADC		FPGA A14 / AD3N / XA_N1
8	ADC		FPGA A16 / AD10N / XA_N2
9	ADC		FPGA B17 / AD2N / XA_N3
10	ADC		FPGA A18 / AD11N / XA_N4
11	Ground	GND
12	Power	3V3

Signal

Role

Net

Also / notes

Pmod JA

GPIO

FPGA C17

GPIO

FPGA D18

GPIO

FPGA E18

GPIO

FPGA G17

Ground

GND

Power

3V3

GPIO

FPGA D17

GPIO

FPGA E17

GPIO

FPGA F18

GPIO

FPGA G18

Ground

GND

Power

3V3

Pmod JB

GPIO

FPGA D14

GPIO

FPGA F16

GPIO

FPGA G16

GPIO

FPGA H14

Ground

GND

Power

3V3

GPIO

FPGA E16

GPIO

FPGA F13

GPIO

FPGA G13

GPIO

FPGA H16

Ground

GND

Power

3V3

Pmod JC

GPIO

FPGA K1

GPIO

FPGA F6

GPIO

FPGA J2

GPIO

FPGA G6

Ground

GND

Power

3V3

GPIO

FPGA E7

GPIO

FPGA J3

GPIO

FPGA J4

GPIO

FPGA E6

Ground

GND

Power

3V3

Pmod JD

GPIO

FPGA H4

GPIO

FPGA H1

GPIO

FPGA G1

GPIO

FPGA G3

Ground

GND

Power

3V3

GPIO

FPGA H2

GPIO

FPGA G4

GPIO

FPGA G2

GPIO

FPGA F3

Ground

GND

Power

3V3

Pmod JXADC (dual analog/digital)

ADC

FPGA A13 / AD3P / XA_P1

ADC

FPGA A15 / AD10P / XA_P2

ADC

FPGA B16 / AD2P / XA_P3

ADC

FPGA B18 / AD11P / XA_P4

Ground

GND

Power

3V3

ADC

FPGA A14 / AD3N / XA_N1

ADC

FPGA A16 / AD10N / XA_N2

ADC

FPGA B17 / AD2N / XA_N3

ADC

FPGA A18 / AD11N / XA_N4

Ground

GND

Power

3V3