Loading source-backed pinouts…
FPGA · Development Board
Digilent Basys 3
The standard intro FPGA teaching board: 16 switches, 16 LEDs, a 4-digit 7-segment display, and VGA.
- GPIO
- SPI
- USB
- JTAG
- Processor
- AMD/Xilinx Artix-7 XC7A35T-1CPG236C
- Logic
- 3.3 V logicTreat as not 5 V tolerant
- Power
- USB-JTAG port or external 4.5–5.5 V via J6 (JP2 selects)
- Format
- Self-contained trainer board with switches, LEDs, 7-segment display
Before you wire
4 cautions- JP1 has three configuration-source positions (SPI flash / JTAG / USB); a wrong jumper after a lab session is the most common 'bitstream won't load' issue.
- The USB host port passes unregulated power to attached devices — external battery packs must stay at 5.5 V max.
- PS/2-over-USB emulation requires FPGA-side pull-ups enabled on DATA/CLK or keyboard/mouse input fails silently.
- Pmod connectors are not impedance- or delay-matched; unsuitable for high-speed signaling.
Pin map
Pin map queued
This board has official references linked, but its in-app connector map still needs a source-backed import.
Source references
Why it matters
- Fully self-contained lab board — switches, LEDs, buttons, 7-segment display, VGA out.
- USB HID host port reads a real keyboard/mouse via an onboard PS/2 emulator.
- Three Pmod ports plus a dedicated XADC Pmod for analog experiments.
- Can self-configure from a FAT32 USB drive without a PC.