LOLIN D1 Mini

LOLIN · D1

Filter pins

Showing 16 of 16 pins

Simplified technical illustration. Pin data is source-backed; verify against the linked documentation before wiring.

Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.

USB connector at top; left column top-to-bottom = odd positions, right column = even.
GPIO0 (D3), GPIO2 (D4), and GPIO15 (D8) are boot-strap pins — wrong pull levels at reset prevent booting.
A0 is limited to 0–3.2 V via onboard voltage divider (the bare ESP8266 ADC is 0–1 V).
D0 / GPIO16 has no PWM, I2C, SPI, or interrupt support and cannot wake the chip from deep sleep.
GPIO is 3.3 V only; 5 V on any GPIO pin will damage the ESP8266.

Full pin list, synchronized with the board drawing.
#	Role	Net	Also / notes
1	System
3	ADC		0–3.2 V via 220 kΩ/100 kΩ divider; bare chip ADC is 0–1 V.
5	GPIO		No PWM, IRQ, or deep-sleep wake.
7	SPI	SPI	HSPI CLK
9	SPI	SPI	HSPI MISO
11	SPI	SPI	HSPI MOSI
13	Alt	SPI	HSPI CS · Boot-strap: must be LOW at reset.
15	Power	3V3
2	UART	UART0	UART0 TX
4	UART	UART0	UART0 RX
6	I2C	I2C	SCL
8	I2C	I2C	SDA
10	Alt		Boot-strap: LOW = flash mode, must be HIGH for normal boot.
12	Alt	UART1	TXD1 · Onboard LED; boot-strap: must be HIGH at reset.
14	Ground	GND
16	Power	5V

Loading source-backed pinouts…

LOLIN · D1

Filter pins

Showing 16 of 16 pins

Simplified technical illustration. Pin data is source-backed; verify against the linked documentation before wiring.

Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.

USB connector at top; left column top-to-bottom = odd positions, right column = even.
GPIO0 (D3), GPIO2 (D4), and GPIO15 (D8) are boot-strap pins — wrong pull levels at reset prevent booting.
A0 is limited to 0–3.2 V via onboard voltage divider (the bare ESP8266 ADC is 0–1 V).
D0 / GPIO16 has no PWM, I2C, SPI, or interrupt support and cannot wake the chip from deep sleep.
GPIO is 3.3 V only; 5 V on any GPIO pin will damage the ESP8266.

Full pin list, synchronized with the board drawing.
#	Role	Net	Also / notes
1	System
3	ADC		0–3.2 V via 220 kΩ/100 kΩ divider; bare chip ADC is 0–1 V.
5	GPIO		No PWM, IRQ, or deep-sleep wake.
7	SPI	SPI	HSPI CLK
9	SPI	SPI	HSPI MISO
11	SPI	SPI	HSPI MOSI
13	Alt	SPI	HSPI CS · Boot-strap: must be LOW at reset.
15	Power	3V3
2	UART	UART0	UART0 TX
4	UART	UART0	UART0 RX
6	I2C	I2C	SCL
8	I2C	I2C	SDA
10	Alt		Boot-strap: LOW = flash mode, must be HIGH for normal boot.
12	Alt	UART1	TXD1 · Onboard LED; boot-strap: must be HIGH at reset.
14	Ground	GND
16	Power	5V