Loading source-backed pinouts…
Board overview
ESP32-C5-DevKitC-1 v1.2
Espressif · ESP32-C5
Pin search cleared
Filter pins
Showing 32 of 32 pins
Simplified diagram, grouped by function — not to physical scale. Pin data is source-backed; verify against the linked documentation.
Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.
Mapped source · ESP32-C5-DevKitC-1 v1.2 header tables and revision details (Espressif)Official- J1 and J3 use Espressif's official v1.2 numbering, which the user guide explicitly ties to schematic v1.2.
- This map applies to v1.2 boards associated with PW-2025-04-0446 and later, not the initial v1.1 header arrangement.
- GPIO-matrix peripherals such as general SPI, I2C, UART, CAN FD, and PWM can be routed to multiple pins; aliases emphasize fixed IO-mux and low-power functions in Espressif's header table.
- The six exposed ADC channels are GPIO1 through GPIO6; ESP32-C5 has no DAC.
All 32 pins
| # | Signal | Role | Net | Also / notes |
|---|---|---|---|---|
| J1 | ||||
| 1 | Power | 3V3 | ||
| 2 | System | CHIP_PU · Active-low chip disable/reset; high enables the chip. | ||
| 3 | Debug | JTAG | MTMS / LP_GPIO2 / LP_UART_RTSN / LP_I2C_SDA / ADC1_CH1 / FSPIQ · MTMS strapping pin; external loading is sampled at reset. | |
| 4 | Debug | JTAG | MTDI / LP_GPIO3 / LP_UART_CTSN / LP_I2C_SCL / ADC1_CH2 · MTDI strapping pin; external loading is sampled at reset. | |
| 5 | GPIO | XTAL_32K_P / LP_GPIO0 / LP_UART_DTRN | ||
| 6 | ADC | XTAL_32K_N / LP_GPIO1 / LP_UART_DSRN / ADC1_CH0 | ||
| 7 | ADC | LP_GPIO6 / ADC1_CH5 / FSPICLK | ||
| 8 | System | FSPID / SDIO_DATA1 · Strapping pin controlling the early-boot JTAG signal source. | ||
| 9 | Alt | PAD_COMP0 / SDIO_DATA0 | ||
| 10 | Alt | PAD_COMP1 / SDIO_CLK | ||
| 11 | SPI | SPI | FSPICS0 / SDIO_CMD | |
| 12 | System | Boot-mode strapping pin; sampled at reset. | ||
| 13 | System | Strapping pin used for SDIO sampling/driving clock-edge configuration. | ||
| 14 | Power | 5V | ||
| 15 | Ground | GND | ||
| 16 | Reserved | No connection on board revision v1.2. | ||
| J3 | ||||
| 1 | Ground | GND | ||
| 2 | UART | UART | GPIO11 / U0TXD · Connected to the onboard USB-to-UART bridge. | |
| 3 | UART | UART | GPIO12 / U0RXD · Connected to the onboard USB-to-UART bridge. | |
| 4 | GPIO | |||
| 5 | GPIO | |||
| 6 | Reserved | SPICS1 · Unavailable with SPI PSRAM; usable as GPIO15 only on a fitted module without PSRAM. | ||
| 7 | System | RGB LED · Boot/ROM-print strapping pin shared with the onboard addressable RGB LED. | ||
| 8 | ADC | MTCK / LP_GPIO4 / LP_UART_RXD / ADC1_CH3 / FSPIHD | ||
| 9 | ADC | MTDO / LP_GPIO5 / LP_UART_TXD / ADC1_CH4 / FSPIWP | ||
| 10 | Reserved | No connection on board revision v1.2. | ||
| 11 | System | BOOT · Boot-mode strapping pin shared with the Boot button and automatic-download circuit. | ||
| 12 | Ground | GND | ||
| 13 | Alt | USB_D+ / SDIO_DATA2 · Shared with the ESP32-C5 native USB Serial/JTAG port. | ||
| 14 | Alt | USB_D- / SDIO_DATA3 · Shared with the ESP32-C5 native USB Serial/JTAG port. | ||
| 15 | Ground | GND | ||
| 16 | Reserved | No connection on board revision v1.2. | ||