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Board overview
Digilent Zybo Z7-20
Digilent · Zybo Z7
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Showing 72 of 72 pins
Simplified diagram, grouped by function — not to physical scale. Pin data is source-backed; verify against the linked documentation.
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Mapped source · Zybo-Z7-Master.xdc — official pin constraints (Digilent/digilent-xdc, GitHub)Official- Zybo Z7-20 has six Pmod ports; the Zybo Z7-10 has five and lacks JB entirely (JB pins are unpopulated on that variant).
- JA, JB, JC, JD, and JE connect to the Zynq PL fabric (3.3 V LVCMOS, fixed — there is no VADJ-style bank voltage jumper on this board). JF connects only to the Zynq PS via MIO pins in MIO Bank 500, which is also fixed 3.3 V.
- JC, JD, and JB are 'High-Speed' Pmods: their series protection resistors are populated as 0-ohm shunts, so driving a pin configured as an output on both ends can create a short. JA (XADC) and JE (Standard) keep 200-ohm series resistors for short protection.
- JF is wired to Zynq PS MIO pins, not PL fabric pins — it can only be driven by the PS's hard peripheral controllers (GPIO/UART/I2C/SPI), never by programmable logic, and its UART/I2C pin order does not match the usual Pmod convention for those interfaces.
- JA doubles as the XADC Pmod: its 4 signal pairs (pins 1/7, 2/8, 3/9, 4/10) can be used as differential analog inputs (max 1 Vpp) to the Zynq's XADC block, or as ordinary 3.3 V digital I/O.
All 72 pins
| # | Signal | Role | Net | Also / notes |
|---|---|---|---|---|
| Pmod JA (XADC-capable) | ||||
| 1 | ADC | N15 / VAUX pair 1 P | ||
| 2 | ADC | L14 / VAUX pair 2 P | ||
| 3 | ADC | K16 / VAUX pair 3 P | ||
| 4 | ADC | K14 / VAUX pair 4 P | ||
| 5 | Ground | GND | ||
| 6 | Power | VCC(3.3V) | ||
| 7 | ADC | N16 / VAUX pair 1 N | ||
| 8 | ADC | L15 / VAUX pair 2 N | ||
| 9 | ADC | J16 / VAUX pair 3 N | ||
| 10 | ADC | J14 / VAUX pair 4 N | ||
| 11 | Ground | GND | ||
| 12 | Power | VCC(3.3V) | ||
| Pmod JB (Zybo Z7-20 only, PL, high-speed) | ||||
| 1 | GPIO | V8 | ||
| 2 | GPIO | W8 | ||
| 3 | GPIO | U7 | ||
| 4 | GPIO | V7 | ||
| 5 | Ground | GND | ||
| 6 | Power | VCC(3.3V) | ||
| 7 | GPIO | Y7 | ||
| 8 | GPIO | Y6 | ||
| 9 | GPIO | V6 | ||
| 10 | GPIO | W6 | ||
| 11 | Ground | GND | ||
| 12 | Power | VCC(3.3V) | ||
| Pmod JC (PL, high-speed) | ||||
| 1 | GPIO | V15 | ||
| 2 | GPIO | W15 | ||
| 3 | GPIO | T11 | ||
| 4 | GPIO | T10 | ||
| 5 | Ground | GND | ||
| 6 | Power | VCC(3.3V) | ||
| 7 | GPIO | W14 | ||
| 8 | GPIO | Y14 | ||
| 9 | GPIO | T12 | ||
| 10 | GPIO | U12 | ||
| 11 | Ground | GND | ||
| 12 | Power | VCC(3.3V) | ||
| Pmod JD (PL, high-speed) | ||||
| 1 | GPIO | T14 | ||
| 2 | GPIO | T15 | ||
| 3 | GPIO | P14 | ||
| 4 | GPIO | R14 | ||
| 5 | Ground | GND | ||
| 6 | Power | VCC(3.3V) | ||
| 7 | GPIO | U14 | ||
| 8 | GPIO | U15 | ||
| 9 | GPIO | V17 | ||
| 10 | GPIO | V18 | ||
| 11 | Ground | GND | ||
| 12 | Power | VCC(3.3V) | ||
| Pmod JE (PL, standard) | ||||
| 1 | GPIO | V12 | ||
| 2 | GPIO | W16 | ||
| 3 | GPIO | J15 | ||
| 4 | GPIO | H15 | ||
| 5 | Ground | GND | ||
| 6 | Power | VCC(3.3V) | ||
| 7 | GPIO | V13 | ||
| 8 | GPIO | U17 | ||
| 9 | GPIO | T17 | ||
| 10 | GPIO | Y17 | ||
| 11 | Ground | GND | ||
| 12 | Power | VCC(3.3V) | ||
| Pmod JF (PS MIO, not PL) | ||||
| 1 | GPIO | Zynq PS MIO pin, MIO Bank 500 (3.3 V). Accessible only via PS peripheral cores (GPIO/UART/I2C/SPI), never from programmable logic. | ||
| 2 | GPIO | PS MIO, MIO Bank 500 (3.3 V). | ||
| 3 | GPIO | PS MIO, MIO Bank 500 (3.3 V). | ||
| 4 | GPIO | PS MIO, MIO Bank 500 (3.3 V). | ||
| 5 | Ground | GND | ||
| 6 | Power | VCC(3.3V) | ||
| 7 | GPIO | PS MIO, MIO Bank 500 (3.3 V). | ||
| 8 | GPIO | PS MIO, MIO Bank 500 (3.3 V). | ||
| 9 | GPIO | PS MIO, MIO Bank 500 (3.3 V). | ||
| 10 | GPIO | PS MIO, MIO Bank 500 (3.3 V). | ||
| 11 | Ground | GND | ||
| 12 | Power | VCC(3.3V) | ||