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Board overview
Digilent Arty S7-50
Digilent · Arty
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Showing 105 of 105 pins
Simplified diagram, grouped by function — not to physical scale. Pin data is source-backed; verify against the linked documentation.
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Mapped source · Arty-S7-50-Master.xdc — official pin constraints (Digilent/digilent-xdc, GitHub)Official- This map is scoped to the Arty S7-50 Rev. E (XC7S50). The smaller Arty S7-25 (XC7S25) uses the same connector pinout but a smaller FPGA — check your silkscreen if targeting placement/timing.
- All Pmod and shield digital pins are fixed 3.3 V LVCMOS — there is no VADJ-style bank voltage jumper on this board. Digilent's manual states the Arty S7 is not compatible with shields that output 5 V digital or analog signals.
- Pmod JC and JD share package pins with shield digital I/O IO34-IO41 and IO26-IO33 respectively — do not drive both a Pmod device and the corresponding shield pins at the same time.
- Shield IO10-IO13 (SPI: SS/MOSI/MISO/SCK) share FPGA pins with the dedicated SPI header; the manual explicitly warns not to use both at once.
- Shield A0-A5 are single-ended XADC inputs (0-3.3 V); A6-A9 are differential XADC pairs (0-1.0 V) and share pins with digital ck_a6-ck_a9. A10/A11 (ck_a10/ck_a11) are digital-only and cannot be used as analog inputs.
- A0-A5 route to TWO different FPGA balls depending on mode: through a resistor divider to the XADC (vaux0/1/9/2/10/11 at B13/A13, B15/A15, E12/D12, B17/A17, C17/B18, E16/E17) for analog, or directly to G13, B16, A16, C13, C14, D18 for digital I/O. The inner header A6-A9 is different — there, analog and digital modes share the SAME ball. Digilent's master XDC warns: do not apply both constraint sets at once.
All 105 pins
| # | Signal | Role | Net | Also / notes |
|---|---|---|---|---|
| Pmod JA | ||||
| 1 | GPIO | L17 | ||
| 2 | GPIO | L18 | ||
| 3 | GPIO | M14 | ||
| 4 | GPIO | N14 | ||
| 5 | Ground | GND | ||
| 6 | Power | VCC(3.3V) | ||
| 7 | GPIO | M16 | ||
| 8 | GPIO | M17 | ||
| 9 | GPIO | M18 | ||
| 10 | GPIO | N18 | ||
| 11 | Ground | GND | ||
| 12 | Power | VCC(3.3V) | ||
| Pmod JB | ||||
| 1 | GPIO | P17 | ||
| 2 | GPIO | P18 | ||
| 3 | GPIO | R18 | ||
| 4 | GPIO | T18 | ||
| 5 | Ground | GND | ||
| 6 | Power | VCC(3.3V) | ||
| 7 | GPIO | P14 | ||
| 8 | GPIO | P15 | ||
| 9 | GPIO | N15 | ||
| 10 | GPIO | P16 | ||
| 11 | Ground | GND | ||
| 12 | Power | VCC(3.3V) | ||
| Pmod JC (shared with shield IO34-IO41) | ||||
| 1 | GPIO | U15 / ck_io41 | ||
| 2 | GPIO | V16 / ck_io40 | ||
| 3 | GPIO | U17 / ck_io39 | ||
| 4 | GPIO | U18 / ck_io38 | ||
| 5 | Ground | GND | ||
| 6 | Power | VCC(3.3V) | ||
| 7 | GPIO | U16 / ck_io37 | ||
| 8 | GPIO | P13 / ck_io36 | ||
| 9 | GPIO | R13 / ck_io35 | ||
| 10 | GPIO | V14 / ck_io34 | ||
| 11 | Ground | GND | ||
| 12 | Power | VCC(3.3V) | ||
| Pmod JD (shared with shield IO26-IO33) | ||||
| 1 | GPIO | V15 / ck_io33 | ||
| 2 | GPIO | U12 / ck_io32 | ||
| 3 | GPIO | V13 / ck_io31 | ||
| 4 | GPIO | T12 / ck_io30 | ||
| 5 | Ground | GND | ||
| 6 | Power | VCC(3.3V) | ||
| 7 | GPIO | T13 / ck_io29 | ||
| 8 | GPIO | R11 / ck_io28 | ||
| 9 | GPIO | T11 / ck_io27 | ||
| 10 | GPIO | U11 / ck_io26 | ||
| 11 | Ground | GND | ||
| 12 | Power | VCC(3.3V) | ||
| Shield outer digital (IO0-IO9) | ||||
| 1 | GPIO | L13 | ||
| 2 | GPIO | N13 | ||
| 3 | GPIO | L16 | ||
| 4 | PWM | R14 | ||
| 5 | GPIO | T14 | ||
| 6 | PWM | R16 | ||
| 7 | PWM | R17 | ||
| 8 | GPIO | V17 | ||
| 9 | GPIO | R15 | ||
| 10 | PWM | T15 | ||
| Shield SPI header (IO10-IO13) | ||||
| 1 | SPI | SPI | H16 · Shares an FPGA pin with the dedicated SPI header's SS; do not use both simultaneously. | |
| 2 | SPI | SPI | H17 | |
| 3 | SPI | SPI | K14 | |
| 4 | SPI | SPI | G16 | |
| Shield outer analog (A0-A5, single-ended) | ||||
| 1 | ADC | B13/A13 (analog vaux0_p/n) / G13 (digital ck_a0) · Analog and digital modes land on DIFFERENT FPGA balls. Constrain to B13/A13 for XADC analog input, or to G13 for digital I/O — never both. | ||
| 2 | ADC | B15/A15 (analog vaux1_p/n) / B16 (digital ck_a1) · Analog B15/A15, digital B16 — different balls; use one constraint set only. | ||
| 3 | ADC | E12/D12 (analog vaux9_p/n) / A16 (digital ck_a2) · Analog E12/D12, digital A16 — different balls; use one constraint set only. | ||
| 4 | ADC | B17/A17 (analog vaux2_p/n) / C13 (digital ck_a3) · Analog B17/A17, digital C13 — different balls; use one constraint set only. | ||
| 5 | ADC | C17/B18 (analog vaux10_p/n) / C14 (digital ck_a4) · Analog C17/B18, digital C14 — different balls; use one constraint set only. | ||
| 6 | ADC | E16/E17 (analog vaux11_p/n) / D18 (digital ck_a5) · Analog E16/E17, digital D18 — different balls; use one constraint set only. | ||
| Shield inner analog (A6-A9, differential) + A10/A11 (digital-only) | ||||
| 1 | ADC | B14 / vaux8_p · Differential pair with A7 (0-1.0 V). | ||
| 2 | ADC | A14 / vaux8_n | ||
| 3 | ADC | D16 / vaux3_p · Differential pair with A9 (0-1.0 V). | ||
| 4 | ADC | D17 / vaux3_n | ||
| 5 | GPIO | D14 · Digital I/O only — cannot be used as an analog input. | ||
| 6 | GPIO | D15 · Digital I/O only — cannot be used as an analog input. | ||
| Shield inner digital (IO26-IO41, shared with JD/JC) | ||||
| 26 | GPIO | U11 / JD10 | ||
| 27 | GPIO | T11 / JD9 | ||
| 28 | GPIO | R11 / JD8 | ||
| 29 | GPIO | T13 / JD7 | ||
| 30 | GPIO | T12 / JD4 | ||
| 31 | GPIO | V13 / JD3 | ||
| 32 | GPIO | U12 / JD2 | ||
| 33 | GPIO | V15 / JD1 | ||
| 34 | GPIO | V14 / JC10 | ||
| 35 | GPIO | R13 / JC9 | ||
| 36 | GPIO | P13 / JC8 | ||
| 37 | GPIO | U16 / JC7 | ||
| 38 | GPIO | U18 / JC4 | ||
| 39 | GPIO | U17 / JC3 | ||
| 40 | GPIO | V16 / JC2 | ||
| 41 | GPIO | U15 / JC1 | ||
| Shield I2C and IO42 | ||||
| 1 | I2C | I2C | J14 · Requires a pull-up; J4 can connect the onboard pull-up. | |
| 2 | I2C | I2C | J13 · Requires a pull-up; J4 can connect the onboard pull-up. | |
| 3 | GPIO | K13 / ck_ioa | ||
| Shield dedicated XADC and references | ||||
| 1 | ADC | J10 / VP_0 · Dedicated XADC differential positive input; 0-1.0 V. | ||
| 2 | ADC | K9 / VN_0 · Dedicated XADC differential negative input; 0-1.0 V. | ||
| 3 | Ground | XGND | VREFN · XADC analog ground reference. | |
| 4 | Power | XVREF | VREFP · 1.25 V, 25 mA XADC reference rail; not general-purpose 3.3 V power. | |
| Shield power header | ||||
| 1 | Reserved | Not connected. | ||
| 2 | Power | IOREF | Fixed to the board's 3.3 V rail. | |
| 3 | System | C18 · Reset button/FPGA reset net; also FTDI DTR when JP2 is shorted. | ||
| 4 | Power | 3V3 | ||
| 5 | Power | 5V | ||
| 6 | Ground | GND | ||
| 7 | Ground | GND | ||
| 8 | Power | VIN | Parallel with the J12 external power input; follow the board's input-voltage limits. | |