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Linux SBC · SBC
Radxa ROCK 3A (hardware V1.3/V1.31)
A Rockchip RK3568 SBC in the Raspberry Pi footprint with an M.2 slot and a 40-pin header, aimed at NAS, edge, and general Linux use.
Processor
Rockchip RK3568 — quad-core Cortex-A55 @ 2.0 GHz with Mali-G52 GPU and a 0.8 TOPS NPU
Logic
3.3 V GPIO (5 V tolerance not documented by Radxa)
Power
USB-C power delivery, or the header 5 V pins
Format
Pi-sized SBC with a 40-pin GPIO header
Check before wiring
- Revision-critical: the V1.2 board and the V1.3/V1.31 board have different 40-pin headers. This entry is the V1.3/V1.31 map. On V1.2, pin 7 is GPIO3_B7, pin 16 is GPIO3_A1, pin 17 is GPIO0_C1 (UART0_TX) rather than +3.3 V, pin 22 is the ADC input ADC_IN5, pin 27 is GPIO0_B6, pin 28 is GPIO0_B5, and pin 37 is GPIO3_C0. Check the silkscreen before wiring.
- GPIO is 3.3 V and Radxa publishes no 5 V tolerance figure — do not drive the header from 5 V logic.
- Pins 8 and 10 carry the UART2 debug console by default; using them as general I/O means giving up serial console access.
- USB 2.0 on pins 27/28 is not available as shipped — it requires removing R90526/R90527 and adding R90536/R90537.
- Pin 17 supplies +3.3 V on this revision. Wiring it as a signal because a V1.2 pinout said GPIO0_C1 would short a rail.
Interfaces
GPIOI2CSPIUARTADCPWMCANUSBPCIeEthernet
Source-backed connector
Interactive pin map
Pin map
Connector
40-pin GPIO header (hardware V1.3/V1.31)
Component side up, 40-pin GPIO header along the top edge
Simplified technical illustration. Pin data is source-backed; verify against the linked documentation before wiring.
Hover, tap, or focus a pad to inspect a pin. Use arrow keys to move between pins.
- This map is the V1.3/V1.31 revision. Radxa publishes a separate, different table for hardware V1.2 — check the silkscreen revision before wiring.
- GPIO is 3.3 V. Radxa publishes no 5 V tolerance figure for this header.
- Pins 8 and 10 (UART2) are the debug console by default; Radxa colours them as reserved for that purpose.
- USB 2.0 on pins 27 and 28 is not usable as shipped — it needs a board rework (remove R90526/R90527, add R90536/R90537).
- Alternate functions are listed as aliases in the vendor's Function1-Function4 order.
All 40 pins (table)
| # | Signal | Role | Net | Also / notes |
|---|---|---|---|---|
| 1 | Power | 3V3 | ||
| 3 | I2C | I2C | I2C3_SDA_M0 / UART3_RX_M0 / CAN1_RX_M0 / GPIO 32 | |
| 5 | I2C | I2C | I2C3_SCL_M0 / UART3_TX_M0 / CAN1_TX_M0 / GPIO 33 | |
| 7 | I2C | I2C | I2C2_SCL_M0 / PWM1_M1 / GPIO 13 · Differs from hardware V1.2, where pin 7 is GPIO3_B7. | |
| 9 | Ground | GND | ||
| 11 | UART | UART | PWM14_M0 / UART7_TX_M1 / GPIO 116 | |
| 13 | UART | UART | PWM15_IR_M0 / UART7_RX_M1 / GPIO 117 | |
| 15 | UART | UART | PWM1_M0 / UART0_RX / GPIO 16 | |
| 17 | Power | 3V3 | On hardware V1.2 this position is GPIO0_C1 (UART0_TX), not a power pin. | |
| 19 | SPI | SPI | PWM15_IR_M1 / SPI3_MOSI_M1 / CAN1_TX_M1 / GPIO 147 | |
| 21 | SPI | SPI | PWM12_M1 / SPI3_MISO_M1 / UART9_TX_M1 / GPIO 149 | |
| 23 | SPI | SPI | PWM14_M1 / SPI3_CLK_M1 / CAN1_RX_M1 / GPIO 146 | |
| 25 | Ground | GND | ||
| 27 | I2C | I2C | I2C1_SDA / CAN0_RX_M0 / USB_DP / GPIO 12 · Differs from hardware V1.2 (GPIO0_B6). USB use requires the documented resistor rework. | |
| 29 | UART | UART | UART8_TX_M1 / GPIO 95 | |
| 31 | UART | UART | UART8_RX_M1 / GPIO 96 | |
| 33 | UART | UART | SPI1_CLK_M1 / UART5_RX_M1 / GPIO 115 | |
| 35 | GPIO | GPIO 100 | ||
| 37 | ADC | On hardware V1.2 this position is GPIO3_C0 instead, and the ADC input sits on pin 22. | ||
| 39 | Ground | GND | ||
| 2 | Power | +5.0V | ||
| 4 | Power | +5.0V | ||
| 6 | Ground | GND | ||
| 8 | UART | UART | UART2_TXD / GPIO 25 · Debug console by default. | |
| 10 | UART | UART | UART2_RXD / GPIO 24 · Debug console by default. | |
| 12 | GPIO | GPIO 99 | ||
| 14 | Ground | GND | ||
| 16 | I2C | I2C | I2C2_SDA_M0 / PWM2_M1 / GPIO 14 · Differs from hardware V1.2, where pin 16 is GPIO3_A1. | |
| 18 | UART | UART | UART4_TX_M1 / PWM9_M0 / GPIO 106 | |
| 20 | Ground | GND | ||
| 22 | UART | UART | PWM2_M0 / UART0_TX / GPIO 17 · On hardware V1.2 this position is the ADC input ADC_IN5 instead. | |
| 24 | SPI | SPI | PWM13_M1 / SPI3_CS0_M1 / UART9_RX_M1 / GPIO 150 | |
| 26 | SPI | SPI | SPI3_CS1_M1 / GPIO 153 | |
| 28 | I2C | I2C | I2C1_SCL / CAN0_TX_M0 / USB_DM / GPIO 11 · Differs from hardware V1.2 (GPIO0_B5). USB use requires the documented resistor rework. | |
| 30 | Ground | GND | ||
| 32 | UART | UART | UART5_TX_M1 / GPIO 114 | |
| 34 | Ground | GND | ||
| 36 | GPIO | GPIO 98 | ||
| 38 | GPIO | GPIO 102 | ||
| 40 | GPIO | GPIO 101 |
Why it matters
- RK3568 brings a 0.8 TOPS NPU, Mali-G52 GPU, and native gigabit Ethernet.
- Header exposes an unusually rich mux: six UARTs, CAN, SPI3, two I2C buses, seven PWM channels, and an ADC input.
- M.2 slot supports NVMe storage alongside eMMC and microSD.
- Radxa documents both hardware revisions' pin tables side by side, so revision differences are checkable.
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